Info


Time: 5:30 PM - 7:30 PM
Date: Monday, December 4th, 2017
Location: ME 4195, Carleton University
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IEEE Carleton is proud to announce the Fall 2017 FPGA Competition in collaboration with the ELEC3500 instructor, Ralph Mason.

The Digital Electronics (ELEC 3500) course covers the fundamentals of logic gates, circuit timing, and Design with HDL (Hardware Description Language) along with guiding students to create a basic Tug of War game.

The FPGA competition will challenge students to modify their Tug of War implementation by creating new rules or functionalities. They are required to provide a block diagram describing their implementation.

A detained information package can be accessed here:

Google Drive

Students are strongly encouraged to work on their code prior to the competition because they will only have 1 hour before judging begins.

Participation is free, and pizza will be provided to all participants. Winners will be awarded with an IEEE certificate.

Other prizes will be announced later.

Agenda


5:30 - 6:00 PM - Student setup and prepare for demo
6:00 - 6:45 PM - Judges arrive and judging begins shortly after
6:45 - 7:00 PM - Judges evaluate scores and make decision
7:00 - 7:10 PM - Awards
7:10 - 7:30 PM - Networking (Optional)

Registration


Interested in joining us? Click bellow to register.

Click Here To Register

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